The present invention relates to IC test equipment for testing an IC whose steady-state current is far smaller than its operating current, such as a CMOS.
FIG. 1 shows the circuit arrangement of conventional IC test equipment. This test equipment is to test the DC characteristics of an IC under test 100 and has an arrangement in which a known voltage V.sub.S is applied from a voltage source 200 to a power source terminal of the IC under test 100 and a current I.sub.R corresponding to a current I.sub.L flowing through the IC 100 is detected by a current detector 300.
The current detector 300 comprises a current detecting resistor R.sub.M connected in series between the voltage source 200 and the IC under test 100 and a differential amplifier 301 for extracting voltage which is developed across the resistor R.sub.M in proportion to the current I.sub.R. The output voltage of the differential amplifier 301 is converted by an A-D converter 302 into a digital value. A feedback circuit 400 includes an operational amplifier 402 forming a voltage-follower amplifier. By the feedback circuit 400 the same voltage as that V.sub.S to be applied to the IC under test 100 is fed back to an operational amplifier 201 of the voltage source 200, causing it to operate so that a voltage Vi from a reference voltage source 202 is applied accurately as the voltage V.sub.S to the IC under test 100. Reference numeral 500 indicates a guard amplifier.
The guard amplifier 500 is also a voltage-follower amplifier, which is supplied with the applied voltage V.sub.S of the IC under test 100 detected by the feedback circuit 400 and outputs the same voltage as the input one. The guard amplifier 500 is provided for driving by its output the feedback circuit 400 so that the potential of an outer conductor 501 of a cable 502 used as an input line 401 of the feedback circuit 400 becomes equal to the potential V.sub.S of the input line 401, thereby excluding the influence of the stray capacitance and insulating resistance of the cable 502 to ensure the feedback of the correct voltage V.sub.S to the voltage source 200.
A smoothing capacitor 600 is connected in parallel to the IC under test 100, for smoothing fluctuations in the applied voltage V.sub.S which are caused by the operation of the IC under test 100. When the IC under test 100 is a CMOS type IC, only a very slight current flows therethrough during its quiescent period, whereas when it is driven, a current flowing therethrough is about several thousands times larger. For example, a CMOS memory which is written and read out at a clock period consumes current pulsewise accordingly.
In measurements of the DC characteristic (i.e. an applied voltage vs. power consumption variation characteristic) of such an IC during its operation, when the IC under test 100 dissipates current pulsewise as mentioned above, charges stored in the smoothing capacitor 600, which is connected to a so-called test head to which the IC 100 is also connected, are released to prevent a transient voltage drop, smoothing the voltage to be applied to the IC under test 100. The kind and static capacitance of the smoothing capacitor 600 are selected properly in accordance with the operating or performance characteristic of the IC under test 100.
Incidentally, the smoothing capacitor 600 is effective for a so-called function test of measuring current flowing through the IC under test 100 being operated while applying voltage thereto, but the smoothing capacitor 600 constitutes an obstacle to a so-called static test of measuring current flowing through the IC under test 100 being held quiescent while applying voltage thereto and determining whether or not the current is within a given limit range.
That is, the IC under test 100 is subjected to the static test in which a predetermined power source voltage is applied to the power source terminal of the IC 100 without operating it and it is determined whether or not current flowing therethrough at that time is within a predetermined limit range. In this static test, when the voltage Vi is applied to the IC 100 from the voltage source 200 as shown in FIG. 2A, the current I.sub.R flowing through the current detector 300 is the sum of the current I.sub.L flowing to the IC under test 100 and a charging current I.sub.CL flowing to the smoothing capacitor 600 as shown in FIG. 2B. Since the static test is intended to measure the current I.sub.L which flows through the IC under test 100, a decision unit (not shown) reads out the value of the current I.sub.L from the A-D converter 302 after the charging current I.sub.CL to the smoothing capacitor 600 returns to zero.
The smoothing capacitor 600 can be generally expressed by an equivalent circuit depicted in FIG. 3, and the total current I which flows through the capacitor 600 when a DC voltage is applied thereto is given by the following expression: ##EQU1## where V is the applied voltage, R an equivalent series resistance (an internal resistance of the power source 20), C the electrostatic capacitance of the capacitor, Q.sub.p polarization charges of the capacitor, and r the insulation resistance of the capacitor. The current I decreases with time t and, after a sufficient elapsed time, reaches a constant value.
The first term I.sub.c of the above expression is the charging current of the capacitor of the electrostatic capacitance C. The second term I.sub.d is called a dielectric current, which depends on the kind of the dielectric of the capacitor and the electric field intensity applied thereto. The third term I.sub.r is a leakage current of the capacitor by its insulation resistance r. Usually, the relaxation time of the capacitor is so long that it is difficult to accurately measure the third term I.sub.r based on the insulation resistance r. In general, the ratio between the total current value I one to two minutes after the voltage application and the applied voltage V is defined as the insulation resistance from the practical point of view.
Since much time is taken until the charging/discharging current of the capacitor becomes stable as mentioned above, waiting time inevitably increases for an accurate measurement of the current I.sub.L flowing through the IC under test 100. This constitutes an obstacle to testing of many ICs.